<DIV>Hi, all</DIV>
<DIV> There is no Verilog lexer class in Qscintilla2, so I write a new lexer class for verilog named as "qscilexerverilog.cpp" and "qscilexerverilog.h". But the blockStart and blockEnd for verilog are "begin" and "end", when I input "begin" and "end", they cannot auto indent. Is there anyone can solve the problem. Thanks<BR><BR></DIV><br><!-- footer --><br><span title="neteasefooter"/><hr/>
<a href="http://www.yeah.net">网易邮箱,中国第一大电子邮件服务商</a>
</span>